FIG. 1 shows a diagram of an architecture for a random access memory implemented on a semiconductor chip. As observed in FIG. 1, the memory architecture includes a “slice” of multiple storage cells each of which store a bit of information for a particular bit line. The memory includes a number (N) of such slices equal to the bit width of the words that are read/written from/to the memory. During a read or write operation one, same positioned storage cell in each slice is activated. In the case of a read the activated storage cell provides a bit of information on its corresponding bit line. In the case of a write the activated storage cell receives a bit of information on its corresponding bit line.
Which particular same positioned storage cell is to be activated in each of the slices by any particular memory access is determined by the address decoder. Here, the address decoder receives an incoming address and, in response, activates one of the wordlines. As each wordline is coupled to a same positioned storage cell across all of the slices, the activation of one wordline in response to an address effectively enables one storage cell for each bit of the incoming/outgoing data word. A single memory chip may include just one or multiple instances of the architecture observed in FIG. 1. In the case of the later, the process of address decoding may include activating and/or deactivating whole sections of the memory that conform to the architecture of FIG. 1.